1. Field of the Invention
This invention relates to the planarizing of integrated circuit structures. More particularly, this invention relates to an improved method for forming highly planarized oxide portions in integrated circuit structures.
2. Description of the Related Art
In the conventional construction of integrated circuit structures, field oxide, for example, is usually grown on and into the surface of the silicon substrate to provide oxide insulation between adjacent active devices by masking the active device regions of the substrate and then oxidizing the remaining portions of the substrate.
In the formation of such oxide regions by oxidation of the silicon substrate, that is, by oxide growth rather than by deposition, the oxide grows down into the substrate as well as extending upwardly from the surface. For example, when growing an oxide layer of about one micron thickness, the oxide growth will extend down into the substrate about half the distance, that is, extend down about 0.5 micron below the original silicon substrate surface and also extend about 0.5 micron above the original silicon substrate surface, due to the fact that a given number of silicon atoms in crystalline silicon occupies less volume than the oxide of the same number of silicon atoms.
While this phenomena changes the vertical topology of the integrated circuit structure somewhat, the greater problem is that this expansion of the oxide volume also occurs laterally as well as vertically. Thus, as shown in the prior art structure shown in FIG. 1, the field oxide grown in the unmasked regions of the substrate also extends partially into the masked regions of the substrate with both the downwardly and upwardly extent of the oxide tapering off the further the oxide extends laterally, thus forming what is known in the industry as a "bird's beak".
This "bird's beak" region then narrows the active region of the substrate in between the field oxide portions in which active devices can be constructed, as shown in FIG. 1, down to a width x with the width of the mask minus x representing the area of lateral encroachment of the grown oxide. To remedy this, the dimensions of the mask must be altered to accommodate this encroachment, i.e., the openings for the field oxide must be made smaller.
This, in turn, becomes a problem as the density of integrated circuit structures increase with VLSI. When the lines and spaces, for example, become less than one micron, problems of lithography occur. Furthermore, there may be yet further encroachment if the field implant, i.e., the doping beneath the field oxide, laterally migrates with the field oxide as it grows, thus reducing the active device region still further.
The problems associated with "growing" field oxide regions in an integrated circuit structure has been recognized and attempts have been made to remedy these problems. For example, Chen et al, in an article entitled "A FULLY RECESSED FIELD ISOLATION TECHNOLOGY USING PHOTO-CVD OXIDE", published in IDEM 82 at pp. 233-236, discuss the use of a photoresist layer to etch a groove which is then filled with a photox-CVD oxide (photox) before removing the photoresist mask. Excess "photox" is then removed with the photoresist by liftoff.
Shibata et al, in an article entitled "A SIMPLIFIED BOX (BURIED-OXIDE) ISOLATION TECHNOLOGY FOR MEGABIT DYNAMIC MEMORIES", published in IDEM 83 at pp 27-30, discuss forming isolation oxide by refilling anisotropically etched recesses in silicon substrates with deposited oxide. The original BOX process used two steps, a plasma SiO.sub.2 lift-off in the first step and redeposition of CVD SiO.sub.2 followed by planarization etch-back in the second step. The authors noted that this procedure works satisfactorily for recesses narrow in width, but fails to leave field oxide in wide open areas. The authors suggest using two resist layers with the first resist providing a mask over the oxide in the wide open areas and the second resist layer apparently acting as a planarizing layer.
In parent U.S. application Ser. No. 193,478, cross reference to which is hereby made, there is described and claimed a more satisfactory way to form highly planarized field oxide regions between active regions in the substrate while eliminating the formation of the "bird's beak" encroachment experienced with prior art field oxide growth.
The method described and claimed in that application utilized a mechanically polishable planarization layer, such as a polysilicon layer, which is applied over an oxide layer and then polished down to the highest level of the oxide. The exposed oxide is then etched down to a predetermined level above the underlying integrated circuit structure after which the remaining polysilicon is removed by a further polishing step. The oxide may then be etched down to the level of the highest portions of the underlying integrated circuit structure.
The result is a highly planarized field oxide type separation between active regions, such as, for example, either active devices formed in the substrate or between stepped regions in an integrated circuit structure such as those which occur when conductive lines are formed over the substrate, whereby the topology of the resulting structure will minimize formations of such steps or other nonplanar structures, i.e., will result in a highly planarized integrated circuit structure.
While this method has been found to provide highly planarized structures in most instances, the use of a polishing step to planarize the polysilicon layer can result in problems when the underlying oxide portions are very wide, i.e., over 200 microns in width, because the polishing means are usually insufficiently flat to prevent some of the oxide under the polysilicon from being exposed in such wide areas.